The present invention relates to non-volatile flash memory devices, and more particularly, to a method of programming multi-level flash memory cells.
Multi-level, or multi-bit, flash memory cells provide a solution for increasing the amount of data that can be stored on a memory device without consuming more space. Whereas a single-bit cell can store only two states, “on” and “off” (typically labeled “0” and “1”), a cell having n bits and using binary encoding is capable of storing up 2n states. FIG. 1 shows a multi-bit cell as known in the art, generally labeled 10. The cell 10 has symmetrical source/drain regions 16 and 18 in connection with a semiconductor channel 20. The channel 20 and a gate 14 are separated from a charge trapping layer 12 by oxide regions 13 and 15, respectively. In this configuration, the left side of the charge trapping layer 12 is designated as the “left bit” 22, and the right side as the “right bit” 24.
As can be seen in FIG. 2, since the illustrated cell 10 has two bits, it may store up to 22, or 4, states (“11”, “01” “10”, and “00”). Since accumulation of charge is the key to multi-bit programming, with more precise charge placement in the charge trapping layer 12, a higher number of bits and states may be achieved in cell 10, such as three bits (23=8 states), four bits (24=16 states), or more. Referring again to FIG. 1, the right bit 24 can be programmed by applying potential to the gate 14 and the region 18 (which serves as the drain) and grounding region 20 (which serves as the source). As electrons flow along the channel, they gain enough energy to tunnel through the oxide layer 13 to the charge trapping layer 12. The electrons tend to gather and are trapped in the portion of the charge trapping layer 12 nearest the drain 18, or the right bit 24. The left bit 22 may be programmed in a similar fashion, with region 16 serving as the drain and region 18 serving as the source.
The accumulation of charge in the right bit 24 alters the threshold voltage of the cell. FIG. 2 shows an example of threshold voltage distribution among states, as known in the art. The cell 10 is read by applying a potential that falls between the highest value of the most programmed state and the lowest value of the next highest erased state. For example, to read “01” (also referred to as Level 1 for purposes of illustration), a potential must be applied to the cell that is between the right-most point of the Level 1 distribution and the left-most point of the Level 2 distribution. This region can be referred to as a “read window”. Methods of reading multi-bit cells are disclosed in detail in U.S. Pat. No. 6,011,725, which is incorporated herein by reference.
It is critically important when programming not to significantly overshoot the threshold voltage. An overshoot may result in a read error of the cell. Programming distributions seen in FIG. 2 (as opposed to single points) are the result of overshoot. The further the program cycle can overshoot the target threshold voltage, the wider the distribution will be. In order to most accurately program multi-bit cells, incremental stepping of the drain voltage is typically implemented. Uniform pulses are applied to the drain. Usually a program pulse is followed by a read operation to verify the level of the cell. As the desired threshold voltage is approached, the voltage step of the pulse is decreased. This still results in relatively wider programming distributions. The wider the distributions, the smaller the read windows. Applying potential to the cell invariably affects both bits due to a phenomenon known as the “second bit effect”. Thus, applying a read potential to one bit could increase the charge on the other bit. With small read windows, that extra charge could be enough to bump the cell up to the next programmed state. In addition, if more states are desired for the cell, the margin for programming and read error shrinks rapidly.
Another prior art programming method, taking programming to Level 1 as an example, is illustrated in FIG. 3. During Step 1, the potential applied over a bit line to the drain (indicated as VPPD) is stepped incrementally while the potential applied over a word line to the gate (VCVP) is held constant. For example, when programming to Level 1, once the threshold voltage (Vt) reaches a cue level (PV1′), which is some ΔV below the target voltage (PV1), the method switches to Step 2. In Step 2, the gate voltage is reduced and then stepped incrementally while the drain potential is held constant until the end of the programming cycle. The purpose of the gate potential stepping is to slow down the program speed and thus tighten the programming distributions. However, the circuitry required to perform these operations becomes much more complex and burdensome.
It is therefore desirable to use a method for programming a multi-bit cell that reduces the programming distributions and expands the read windows without requiring complex circuitry and without altering the gate potential.